Station Unit Data Master

Hardware Modification Record

Last change to this page: 991125

Contents:

DIM - Data Input Module

TRM - Track Recovery Module

CRM - Channel Recovery Module

PCM - Phase Cal Module

DCM - Delay Control Module

DMM - Delay Memory Module

Data Input Module (DIM) back to contents

Mod State

Date

Description

 Remarks

A

 

Initial Issue

 

 

 

 

 

 

 

Track Recovery Module (TRM) back to contents

Mod State

Date

Description

 Remarks

A

 

Initial Issue

 

B

 

Add a wire link from U57(58) to U45(Q14)

Microcontroller Address Strobe not connected to LED interface Xilinx. The link is not shown on the circuit schematic and is hence not present in the PCB artwork.

C

990719
  1. Cut the short trace connecting U8/8 to U8/9
  2. Add a wire link from U8/8 to RN9/6

Cure for mis-clocking in TRM (flat lines and offsets) Modification uses redundant trace (EOF) in back plane, and associated buffer on CRM, to provide a separate drive for Track_clk to TRM odd tracks. Existing path supplies even tracks.

New Xilinx also required; PROMs to Issue D.

Implement with CRM change dated 990719

 

 

Channel Recovery Module (CRM) back to contents

Mod State

Date

Description

 Remarks

A

 

Initial Issue

 

B

 

Add a wire link from U25(C3) to R28(2)

TRACK CLOCK connection to gate array needs direct link to improve quality of signal.

C

990719
  1. Cut trace from U10/7 to nearby via
  2. Crop pin U10/13 leaving enough metal on the I/C to attach a wire.
  3. Remove the detached pin and clear the thru-hole.
  4. Using thin, insulated, single strand wire (e.g. wire wrap type) connect U10/13 (i.e. the remaining pin stub) to the via isolated in step 1, passing the wire through the cleared thru-hole.
  5. Add wire link from U10/3 to U10/7
  6. Add wire link from U21/51 to U21/54

Cure for mis-clocking in TRM (flat lines and offsets) Modification uses redundant trace (EOF) in back plane, and associated buffer on CRM, to provide a separate drive for Track_clk to TRM odd tracks. Existing path supplies even tracks.

Implement with TRM change dated 990719

 

Phase Calibration Module (PCM) back to contents

Mod State

Date

Description

 Remarks

A

 
  1. 510Ohm resistor, RN3/1 to RN3/6
  2. 100pF capacitor, U58/V1 to U85/R3

Initial issue of board (mod state A) has these additional components, fitted to the solder side:

 

 

Delay Control Module (DCM) back to contents

Mod State

Date

Description

 Remarks

A

 

Initial Issue

 

B

980709 
  1. Add *100 Ohm resistor between U15(2) and U15(20).
  2. Add *100 Ohm resistor between U15(3) and U15(20).

ROT malfunction with 32MHz station clock

(*value later changed to 200 Ohm - see below)

C

990719
  1. See termination pull-up resistors soldered to pins 2 and 3 of U15, change them to 220 Ohm; these two pins are systick and stnclk inputs;
  2. Find pin15 of U15 and cut the track just close to this pin, solder this track to pin14 with a short (2-3mm) wire;
  3. Find pin6 of U15 and connect it to pin9 of U15 with 12mm insulated wire;
  4. Solder 220 Ohm pull-ups to pins of U54 on solder side of board:

83 - systick
35 - stnclk
78 - fpgaclk

use near-by +5V pin of bypass capacitors as VCC.

 Route FPGA_Clk to DMMs via an independant buffer. This modification cures a number of bugs apparently caused by cross talk in this line.

 

Implement with DMM changes dated 990719; ModState B

 

 

 

Delay Memory Module (DMM) back to contents

Mod State

Date

Description

 

A

 

Initial Issue

 

B

990719
  1. Fit 47 pF capacitor from pin23 of U32 IDT72200 to ground pin8 of U33 SN74F138.
  2. Identify input buffers U17 74FCT540 and U18 74FCT541 on solder side of DMMs.
  3. Solder termination resistors: 680 Ohm to +5V and 470 Ohm to 0V to pins 2 and 3 (they are connected together) of U17, that is for Clk_32 which is FPGACLK.
  4. Solder termination resistors: 680 Ohm to +5V and 470 Ohm to 0V to pins 7 and 8 (they are connected together) of U18, that is for BOCF_DM.
  5. Identify jumpers JP3, JP4 and JP5 on component side of DMMs, remove the plug from its current position and put it to short pin1 of JP3 to pin1 of JP4, this will set stnclk delay to 0 when clocking output buffer,

 Route FPGA_Clk to DMMs via an independant buffer. This modification cures a number of bugs apparently caused by cross talk in this line.

Implement with DCM changes dated 990719; ModState C

 

Station Unit pages are maintained by Steve Parsley