Station Unit Data Master

Microprocessor/Controller Firmware and Software

Last change to this page: 2005.04.04


SUCC Software

Source
Code

Executable

Remarks

SUCC4120sub05

4120sub05ram.hex

For P&G based DPU

4120sub05HAYram.hex

For Honeywell based DPU


Plug-in Module Firmware

Firmware
Module

Device Ref.

PROM
Files

Micro Source

Xilinx Files

Xilinx function

TRM

 

U33,U34

 

G

 

TRM4147

 

6040005D

MkIV Xilinx

6140005A

VLBA Xilinx

DCM

(includes DMM)

U19,U20

 

G

 

DCM4139

 

6010015C

DCM Xilinx

6010016A

DMM Xilinx

CRM(JIVE)

 

"D" series Xilinx

 

 

U42,U43

 

 

 

 

F

 

 

 

 

CRM4135

 

 

 

 

6010010A

Clock generation

6110010A

Multiplex modes

6210010A

Validity bit extraction

6310010A

Cross track parity

6410010A

De-multiplex modes

CRM(HSTCK)

 

"E" series Xilinx

 

 

U42,U43

 

 

 

 

E

 

 

 

 

CRM1WAIT

 

 

 

 

6010010B

Clock generation

6110010B

Multiplex modes

6210010A

Validity bit extraction

6310010B

Cross track parity

6410010B

De-multiplex modes

PCM

 

 

 

 

 

U54,U55

 

 

 

 

 

A

 

 

 

 

 

PCM4131

 

 

 

 

 

6010020B

Master-write/verify

6110020B

Slave-write/verify

6210020E

Master-accumulate

6310020C

Slave-accumulate

6410020C

Pipeline Array 1

6510020C

Pipeline Array 2

 

Notes:

Follow link in first column above for a readme file.

Xilinx devices on the TRM, CRM, PCM and DCM are programmed by the local micro-controller. In general the PROM issue will change if either the micro software or the Xilinx code is changed.

Xilinx archives

The link in the table leads to an ftp directory of the same name. Typically this has three files:

6nnnnnnx.zip = Orcad design archive. Contains schematics and other files needed by Orcad

6n_plot.zip = Orcad schematic plots in HPGL format.

library.zip = library of the Orcad parts used in this design.

A full copy of the source libraries is in SDT4OLD.ZIP

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Station Unit pages are maintained by Steve Parsley