Microprocessor/Controller Firmware and Software
Last change to this page: 2005.04.04
Source |
Executable |
Remarks |
For P&G based DPU |
||
For Honeywell based DPU |
Firmware |
Device Ref. |
PROM |
Micro Source |
Xilinx Files |
Xilinx function |
|
U33,U34
|
|
|
MkIV Xilinx |
|
VLBA Xilinx |
|||||
(includes DMM) |
U19,U20
|
|
|
DCM Xilinx |
|
DMM Xilinx |
|||||
CRM(JIVE)
"D" series Xilinx
|
U42,U43
|
|
|
Clock generation |
|
Multiplex modes |
|||||
Validity bit extraction |
|||||
Cross track parity |
|||||
De-multiplex modes |
|||||
CRM(HSTCK)
"E" series Xilinx
|
U42,U43
|
|
|
Clock generation |
|
Multiplex modes |
|||||
Validity bit extraction |
|||||
Cross track parity |
|||||
De-multiplex modes |
|||||
|
U54,U55
|
|
|
Master-write/verify |
|
Slave-write/verify |
|||||
Master-accumulate |
|||||
Slave-accumulate |
|||||
Pipeline Array 1 |
|||||
Pipeline Array 2 |
Follow link in first column above for a readme file.
Xilinx devices on the TRM, CRM, PCM and DCM are programmed by the local micro-controller. In general the PROM issue will change if either the micro software or the Xilinx code is changed.
Xilinx archives
The link in the table leads to an ftp directory of the same name. Typically this has three files:
6nnnnnnx.zip = Orcad design archive. Contains schematics and other files needed by Orcad
6n_plot.zip = Orcad schematic plots in HPGL format.
library.zip = library of the Orcad parts used in this design.
A full copy of the source libraries is in SDT4OLD.ZIP
Station Unit pages are maintained by Steve Parsley